1. Field of the Invention
The present invention relates to a display device, a liquid crystal display device and a method for producing a display device, and more particularly to a method for fixing a wire breakage in a matrix-type liquid crystal display device.
2. Description of the Related Art
A matrix-type display device includes pixels arranged in a matrix pattern, each pixel being the minimum unit of an image. Among others, active matrix-type liquid crystal display devices including a switching element for each pixel are capable of displaying high-definition images and have been widely used.
An active matrix-type liquid crystal display device includes a plurality of gate lines extending in parallel to one another and a plurality of source lines perpendicular to the gate lines for supplying display signals to the pixels. Therefore, if a wire breakage occurs in a display wire such as a gate line or a source line in an active matrix-type liquid crystal display device, the display signal from the driver circuit is not supplied to the display wire beyond the wire breakage position, thus significantly deteriorating the display quality.
In order to solve the problem, Patent Document 1 (Japanese Laid-Open Patent Publication No. 3-23425), for example, proposes a matrix-type display device including a spare wire that can be connected to at least one of a gate line and a source line, wherein at least one of the gate line and the source line in which a wire breakage has occurred can be connected to the spare wire, whereby it is possible to fix a wire breakage defect.
Moreover, Patent Document 2 (Japanese Laid-Open Patent Publication No. 8-171081) proposes a matrix-type display device including a buffer circuit along a spare wire as described above to thereby compensate for a voltage drop due to the routing of the spare wire and to thus improve the display quality.
Patent Documents 3 (Japanese Laid-Open Patent Publication No. 11-5292) and 4 (Japanese Laid-Open Patent Publication No. 2002-22194) disclose improvements regarding the buffer circuit.
FIG. 15 is an equivalent circuit diagram showing a liquid crystal display device 150 in which it is possible to fix a wire breakage along a source line 102, based on the description of Patent Documents 1 and 2.
The liquid crystal display device 150 includes a liquid crystal display panel 140, a gate driver 109 provided along the left side of the liquid crystal display panel 140, and a source driver 107 provided along the upper side of the liquid crystal display panel 140. The liquid crystal display panel 140 includes an active matrix substrate, a counter substrate provided so as to oppose the active matrix substrate, and a liquid crystal layer interposed between the substrates. Provided on the active matrix substrate are a plurality of gate lines 101 extending in the horizontal direction in the figure and a plurality of source lines 102 extending in the vertical direction in the figure. A thin film transistor (hereinafter abbreviated as a “TFT”) 111, being a switching element, is provided at each intersection between the gate line 101 and the source line 102. The source driver 107 includes output amplifiers 106 each connected to a source line 102, and a buffer circuit 104. Moreover, a first spare wire 103a and a second spare wire 103b are provided, wherein the first spare wire 103a extends perpendicular to the source lines 102 in an area along the upper side of the liquid crystal display panel 140 to be connected to the input side of the buffer circuit 104 in the source driver 107, and the second spare wire 103b extends from the output side of the buffer circuit 104 and passes through the upper side, the right side and the lower side of the liquid crystal display panel 140 to be extending perpendicular to the source lines 102 in an area along the lower side of the liquid crystal display panel 140.
FIG. 16 is an equivalent circuit diagram showing the liquid crystal display device 150, wherein a wire breakage has occurred in the source line 102, and the defect has been fixed by connecting the source lines 102 (102a and 102b) with the spare wires 103 (the first spare wire 103a and the second spare wire 103b).
In FIG. 16, the source line 102 breaks at a wire breakage position X1 to be divided into a source line 102a above the wire breakage position X1 and a source line 102b below the wire breakage position X1. The source line 102a and the first spare wire 103a are connected together at an intersection A1, and the source line 102b and the second spare wire 103b are connected together at an intersection A2. This connection can be made by irradiating the intersections A1 and A2 with a light energy 123 such as laser light from the side of a glass substrate 120 to thereby make a contact hole in an insulating film 119 and to electrically connect the source line 102 with the spare wires 103, as shown in FIG. 17. Thus, a display signal from the output amplifier 106 in the source driver 107 is supplied to the source line 102b below the wire breakage position X1 via an upper portion of the source line 102a, the connection position (intersection) A1, the first spare wire 103a, the buffer circuit 104, the second spare wire 103b, and the connection position (intersection) A2. Thus, even if a wire breakage occurs in a display wire, the display signal from the driver circuit is supplied to the display wire beyond the wire breakage position, i.e., the wire breakage is fixed. The buffer circuit 104 functions as an amplifier for amplifying the display signal for impedance conversion along the spare wire 103 including the first spare wire 103a and the second spare wire 103b. 
However, defect fixing methods as described above do not take into consideration the difference in the magnitude of the capacitance to be the load between an unbroken, normal source line 102 and the broken, divided source lines 102a and 102b. 
The difference in the magnitude of the capacitance will now be described in detail.
FIG. 18 is an equivalent circuit diagram showing capacitances on the source line 102 per pixel.
As shown in FIG. 18, capacitances on the source line 102 include a liquid crystal capacitance Clc, a storage capacitance Ccs, a parasitic capacitance Csg occurring at the intersection between the source line 102 and the gate line 101, a parasitic capacitance CsdA occurring between the source line 102 and the drain electrode of the TFT 111 of the pixel on the right side of the source line 102, a parasitic capacitance CsdB occurring between the source line 102 and the drain electrode of the TFT 111 of the pixel on the left side of the source line 102, etc.
The liquid crystal capacitance Clc and the storage capacitance Ccs are connected to be loads only when a predetermined gate line 101 is selected and the TFT 111 is ON. With an ordinary active matrix-type liquid crystal display device, only one gate line 101 is being selected at any time, whereby the liquid crystal capacitance Clc and the storage capacitance Ccs do not present a heavy load on one source line 102. On the other hand, the remaining parasitic capacitances Csg, CsdA and CsdB are always present irrespective of the selection of the gate line 101, and thus present a heavy load on one source line 102. Specifically, one source line 102 receives the parasitic capacitances Csg, CsdA and CsdB multiplied by the number of gate lines 101, e.g., 768 in an XGA-resolution liquid crystal display device. The magnitude of the parasitic capacitance is not negligible with respect to the display quality of the liquid crystal display device, whereby the output amplifiers 106 and the buffer circuit 104 of the source driver 107 need to be provided with a capacity of accommodating the magnitude of the parasitic capacitance to be the load.
However, in an actual liquid crystal display device, it is not possible to know where a wire breakage of the source line 102 will occur.
For example, in a case where the source line 102 breaks at the wire breakage position X1 distant from the source driver 107 so as to be divided into the source line 102a above the wire breakage position X1 and the source line 102b below the wire breakage position X1, as shown in FIG. 16, the number of the parasitic capacitances Csg, CsdA and CsdB to be the load on the source line 102a is not significantly different from the number of the parasitic capacitances Csg, CsdA and CsdB to be the load on a normal source line 102. Therefore, the load on the source line 102a above the wire breakage position X1 is not significantly different from the load on a normal source line 102. On the other hand, the number of the parasitic capacitances Csg, CsdA and CsdB to be the load on the source line 102b is significantly fewer than the number of the parasitic capacitances Csg, CsdA and CsdB to be the load on a normal source line 102. Therefore, the load on the source line 102b below the wire breakage position X1 is very small as compared with the load on a normal source line 102.
Similarly, in a case where the source line 102 breaks at a wire breakage position X2 very close to the source driver 107 so as to be divided into a source line 102c above the wire breakage position X2 and a source line 102d below the wire breakage position X2, as shown in FIG. 19, the load on the source line 102c is very small as compared with the load on a normal source line 102. On the other hand, the load on the source line 102d is not significantly different from the load on a normal source line 102.
Thus, the load on a source line divided in a wire breakage varies, i.e., the distribution of the parasitic capacitance to be the load varies, depending on the wire breakage position.
FIG. 20 shows an output waveform W1 of a normal source line 102, and an output waveform W2 of the spare wire 103 to which another source line 102 broken in a wire breakage is connected.
In the source driver 107, the load on the output amplifier 106 and the load on the buffer circuit 104 are determined so that a normal source line 102 can be driven normally, as described above. However, if the source line 102 is divided by a wire breakage and the parasitic capacitance to be the load on a divided source line (e.g., the source line 102b) is very small, the waveform may overshoot or undershoot as shown in an output waveform W2 of FIG. 20.
If the degree of overshoot or undershoot is high, a more excessive voltage than a normal source line 102 applies on the liquid crystal layer. For example, with a normally-white liquid crystal display device, for example, pixels along the source line 102 where the wire breakage has occurred are darkened and appear to be a black line. With a normally-black liquid crystal display device, pixels along the source line 102 where the wire breakage has occurred are lightened and appear to be a bright line. Thus, the display quality deteriorates.
The overshoot or undershoot is less likely to influence the display when the resolution of the liquid crystal display device is low and the charging time of each pixel (one horizontal period). However, if the resolution is high (e.g., UXGA), the charging time is short and the overshoot or undershoot will be non-negligible. Moreover, with higher resolutions, the number of the parasitic capacitances Csg, CsdA and CsdB to be the load on the source line 102 also increases, thereby also increasing the difference between the load on a normal source line 102 and the load on a source line (e.g., the source line 102b) divided in a wire breakage.
When the screen size of the liquid crystal display device is increased, the area across which the parasitic capacitances Csg, CsdA and CsdB are formed increases, whereby the difference between the load on a normal source line 102 and the load on a source line 102 divided in a wire breakage will further increase as described above.
Thus, with the recent increase in the resolution and the screen size of a liquid crystal display device, the difference between the load on a normal source line and the load on a source line divided in a wire breakage further increases, thereby increasing the overshoot or undershoot and deteriorating the display quality.